In software defined radio an Analog-to-Digital converter (ADC) needs in order to simplify automatic gain control (AGC) and to relax filtering requirements a speed of at least 200 MSamples/s and as much resolution as is feasible for a power budget of a few mW. In addition, since this ADC also needs to quantize much lower bandwidth standards, a dynamic solution is desirable.
For such high speed ADCs interleaving is widely used. In high speed interleaved ADCs the effective ADC sampling frequency is increased by operating multiple sub-ADCs alternately. Moreover, fully dynamic interleaved ADCs are of special interest, as their total power consumption is independent of the number of parallel channels and the speed requirements for each individual channel are relaxed. However, interleaved ADCs suffer in general from mismatches among channels, gain mismatch and bandwidth mismatch. DC offset and gain mismatch are frequency-independent and can thus easily be calibrated in the digital domain. Bandwidth mismatch is frequency dependent and requires complex algorithms to be calibrated digitally.
Bandwidth mismatch is caused by mismatch among the sampling capacitance and sampling switch resistance of the sampling circuit of the interleaved sub-ADCs. As the sampling capacitance and the sampling switch resistance form a low pass filter, bandwidth mismatch between the sampling circuits causes a different frequency response for each sub-ADC. Thus, the input signal will be attenuated differently, leading to errors at higher frequencies where the resulting low pass filter has a greater attenuation and delay effect on the input signals. Consequently, spurious tones are caused which limit the high frequency input performance of interleaved ADCs.
In addition to bandwidth mismatch between the interleaved sub-ADCs, sampling circuits have to be designed for sufficiently good linearity. Indeed, sampling circuits always introduce harmonic distortion, which in the frequency domain shows up as spurious tones at multiples of the applied signal frequency. Since this distortion is added directly to the sampled voltage, it affects the overall linearity of the converter. In “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter” (A. M. Abo et al., JSSC, Vol. 34, No. 5, May 1999) a bootstrapped sampling switch has been proposed which significantly reduces harmonic distortion introduced by the sampling. This bootstrapped switch approach, or some variation thereof, is used in nearly all ADC designs that target high linearity. The bootstrapped approach ensures signal independent switch resistance by providing an input independent gate-source voltage for the sampling switch.
A highly linear interleaved ADC thus needs to combine excellent harmonic linearity as well as excellent bandwidth matching between interleaved channels. The former can be achieved by designing a bootstrapped sampling switch with a high, signal independent sampling switch gate-source voltage. The latter can be achieved by adjusting the bandwidths of interleaved channels. This adjustment should happen without degrading the harmonic performance of the sampling stage.
FIG. 1 illustrates a typical sampling network 10 for a two-times interleaved ADC comprising a plurality of sampling circuits 1. Each sampling circuit 1 is composed of a bootstrap circuit 2 and a series connection of a sampling switch 11 and a sampling capacitor 12. During the tracking phase (CLKint1,2=1) the sampling switches turn on and the voltage on each sampling capacitor follows the input voltage Vin. Just after the hold phase starts (CLKint1,2=0), the switches 11 turn off and hold the sampled voltage. To obtain good linearity, many high performance ADCs typically use a bootstrap circuit 2 as shown in FIG. 2. During the hold phase (when φ=1), a fixed charge voltage Vch is used to charge the bootstrap capacitor (Cbs) 21 and at the same time the bootstrap output Vbs is tied to the ground to turn off the sampling switch. During the tracking phase the bootstrap capacitor 21 is connected between the switch transistor input and its gate. Due to the charge stored into Cbs the bootstrap output voltage Vbs approximates Vin+Vch. The gate-source voltage Vgs of the switch transistor 11 is thus kept constant (≅Vch). Maintaining constant Vgs reduces the signal dependent non-linearity of the sampling switch by maintaining a constant sampling switch resistance. The bandwidth of sampling circuit 1 is mainly defined by the product of the sampling switch on-resistance (Ron) and sampling capacitance (Cs). Therefore, the mismatch of these sampling circuits among interleaved channels is the main cause of the bandwidth mismatch. If somehow either Ron or Cs or both can be optimized to make the Ron*Cs product the same for all sampling circuits and constant across an input signal frequency range one can assure excellent bandwidth matching and harmonic linearity.
Conventionally, one tries to calibrate bandwidth mismatch by tuning the on-resistance of the sampling switch transistors. A possible implementation is given in US2013/141261. This application discloses a time-interleaved AD converter containing a number of sub-ADC circuits. Each sub-ADC circuit includes a sample-and-hold (S/H) circuit. To adjust the frequency response of each S/H circuit a bootstrap circuit is provided. The bootstrap circuit is used to maintain a relatively constant gate-to-source voltage across the sampling switch and thus to maintain the sample-and-hold circuit linearity. The bootstrap circuit efficiency can be adjusted with trim loads containing a capacitor bank, so that capacitance can be selectively added to the capacitance at the switch gate. Considering the parasitic capacitance (Cpar) connected to the bootstrap output, the gate voltage Vbs of the sampling switch is calculated asVbs=Cbs/(Cbs+Cpar)*(Vin+Vch)  (1)
Changing the capacitance value of either Cbs or Cpar as proposed in US2013/141261 obviously changes Vbs and thus the sampling circuit bandwidth.
There are two issues with this approach. First, adding trimmable loads to Cbs and Cpar inevitably degrades the harmonic performance of the sampling circuit, as the bootstrap circuit is highly dependent on parasitic capacitors on the top plate of Cbs and on the sampling switch gate. Since a trimmable load inevitably increases these parasitics, the harmonic distortion introduced by a bootstrap circuit with these trimmable loads would inevitably be worse than in a bootstrap circuit without such loads. Second, when the sampling switch gate is drawn to ground to implement the sampling instant, this switch injects some charge into the sampling capacitor. Since the injected charge is proportional to Vbs, which contains the term Cbs/(Cbs+Cpar)*Vin, this charge injection causes some channel gain mismatch if Cbs/(Cbs+Cpar) is not the same in both channels. As a result, linearity of the ADC might degrade at some frequencies even while it is optimized at another frequency. Since the effect of gain mismatch is independent of the input frequency, this is especially true at lower frequency input: the interleaving spur after calibration could be significantly degraded and becomes worse than an interleaving spur without calibration. This means the bandwidth mismatch calibration proposed in this prior art document does not work well if good linearity is also required across a wide input frequency range.
U.S. Pat. No. 8,248,282 presents a time-interleaved A/D converter having a track-and-hold (T/H) architecture with tunable bandwidth that can be adjusted from a blind bandwidth mismatch estimation. Each ADC branch comprises a bootstrap circuit coupled to its respective track-and-hold circuit. A controller provides a control voltage to the bootstrap circuit to control a gate voltage of the sampling switch to adjust the sampling switch impedance. The proposed solution primarily tunes the gate voltage of a transistor inserted between the bootstrap capacitor and the gate node of the sampling switch and the source voltage of the transistor disables the switch between the gate node of the sampling switch and the top plate of the bootstrap capacitor. Consequently, the primary tuning mechanism is the resistance between the top plate of the bootstrap capacitor and gate node, which modulates turn-off time of the sampling switch. The sampling switch gate voltage during tracking is only slightly affected, which means this solution does not directly compensate for variation in the on-resistance, but rather tries to compensate its effects.
In “A 12b 1GS/s SiGe BiCMOS Two-Way Time-Interleaved Pipeline ADC” (R. Payne et al., ISSCC2011, pp. 182-184) a bootstrap circuit with a DAC voltage power supply is disclosed. To ensure reliable operation without undue stress on the transistors in the bootstrap circuits, this DAC voltage input must necessarily be smaller than the nominal supply voltage of a given technology. This means that the DAC powering the bootstrap circuit can only tune the sampling bandwidth by reducing the Vch in the above-mentioned equation (1) for Vbs, which also degrades the harmonic linearity of the sampling circuit. Moreover, this approach needs a voltage DAC capable of powering the bootstrap circuit, at the expense of valuable power and area.
Hence, there is a need for a technique for tuning sampling bandwidth in interleaved ADCs which a) does not degrade linearity across an input frequency range of interest, b) does not degrade sampling harmonic distortion by reducing the bootstrap voltage, c) does not require significant circuit overhead, for example additional voltage DACs or other complex circuitry and d) tunes the gate voltage of the sampling switch in track mode to directly change on-resistance of the sampling switches.